The field of invention relates to electronic circuitry in general; and, more specifically, to driver/receiver circuits. Still more particularly, the present invention relates to driver/receiver circuits for use in assisted Gunning transceiver logic (AGTL)-type buses.
Some high-speed electronic applications use assisted Gunning transceiver logic (AGTL) type buses. An AGTL-type bus is a multi-drop bus with resistive bus line terminations. FIG. 1 shows a conventional AGTL-type bus system 10 having 50 xcexa9 resistors 11 and 12, driver/receiver circuits 13-15 and a bus line 16 of an AGTL-type bus. In this example, driver/receiver circuits 13-15 are part of chips or agents (not shown) connected to bus line 16, which is an AGTL+ bus. Each bus line of an AGTL+ bus typically has a characteristic impedance of about 50 xcexa9 (represented by transmission line symbols 16A in FIG. 1). Further, an AGTL+ bus typically operates at 1.5 volts, although other voltages can be used. In this example, driver/receiver circuits 13-15 each provide a 12.5 xcexa9 resistive path to the ground line when driving a logic low signal onto bus line 16.
The elements of system 10 are interconnected as follows. Driver/receiver circuit 13 is connected to an end 17 of bus line 16 and to the ground line. End 17 is resistively terminated with resistor 11, which is connected to a VCC line. Driver/receiver circuit 14 is connected to a node 18 of bus line 16 and to a ground line. Unlike end 17, node 18 is not connected to the VCC line through a 50 xcexa9 resistor. Driver/receiver circuit 15 is connected to an end 19 of bus line 16 and to the ground line. End 19 is connected to the VCC line through resistor 12. The other bus lines of the AGTL-type bus would have similarly placed driver/receiver circuits. Further, in an AGTL+ bus, the resistor is xe2x80x9con-diexe2x80x9d on the chips that are connected at the extremes of the line. In addition, these resistors are xe2x80x9cconstantxe2x80x9d in that they are configured to constantly pull-up the bus line during operation.
Although system 10 can achieve relatively high data rates, the resistive terminations of the AGTL-type bus dissipate power when system 10 is powered, especially when a driver/receiver is pulling a bus line to a logic low level. In addition, the resistance (i.e., the Thevenin equivalent impedance of the 50 xcexa9 resistor and receiver/driver circuit) at each end of a bus line of AGTL-type bus is not well matched with the characteristic impedance of the bus line. For example, when driver/receiver circuit 13 drives a logic low level onto bus line 16, the equivalent impedance of the 12.5 xcexa9 pull-down path of the driver/receiver and the 50 xcexa9 pull-up path of resistor 11 is about 10 xcexa9. This mismatched termination undesirably tends to cause reflections that degrade the signal quality of the signals driven on bus line 16. Still further, in some AGTL-type buses, the resistors are connected externally to the chips. This connection results in a stub between the input buffer of the chip and the termination resistor, which can further degrade the signal quality.